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? 2009 semtech corporation power management 1 us patents: 6,504,422; 6,794,926 typical application circuit sc654 light management unit for 6 leds with sempulsetm interface sc654 in spif gnd out bl1 bl5 c in 2.2 f bl6 c1+ from microprocessor v bat = 2.9 to 5.5v c out 2.2 f c2 2.2 f c1 2.2 f bl2 bl3 bl4 c2+ c1- c2- features input supply voltage range 2.9v to 5.5v very high effi ciency charge pump driver system with three modes 1x, 1.5x and 2x six programmable current sinks 0ma to 25ma up to three led grouping options fade-in/fade-out feature for main led bank charge pump frequency 250khz sempulse single wire interface backlight current accuracy 1.5% typical backlight current matching 0.5% typical led fl oat detection automatic sleep mode (leds off ) i q = 60a (typ.) shutdown current 0.1a (typical) ultra-thin package 2 x 2 x 0.6 (mm) fully weee and rohs compliant applications cellular phones, smart phones, and pdas lcd modules portable media players digital cameras personal navigation devices display/keypad backlighting and led indicators ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the sc654 is a high effi ciency charge pump led driver using semtechs proprietary charge pump technology. performance is optimized for use in single-cell li-ion battery applications. the charge pump provides backlight current utilizing six matched current sinks. the load and supply conditions determine whether the charge pump operates in 1x, 1.5x, or 2x mode. an optional fading feature that gradually adjusts the backlight current is provided to simplify control software. the sc654 uses the proprietary sempulse tm single wire interface to control all functions of the device, including backlight currents. the single wire interface minimizes microcontroller and interface pin counts. the six leds can be grouped in up to three separate banks that can be independently controlled. the sc654 enters sleep mode when all the led drivers are disabled. in this mode, the quiescent current is reduced while the device continues to monitor the sempulse interface. with a 2 x 2 (mm) package and four small capacitors, the sc654 provides a complete led driver solution with a minimal pcb footprint. january 30, 2009
2 pin confi guration marking information ordering information notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) lead-free package only. device is weee and rohs compliant. mlpq-ut-14; 2x2, 14 lead ja = 127c/w sc654 top view 1 2 3 8 9 10 45 6 7 14 13 12 11 bl3 c2+ spif bl2 bl5 bl4 bl1 in out c1+ c1- bl6 gnd c2- device package SC654ULTRT (1)(2) mlpq-ut-14 22 sc654evb evaluation board ... 0w yw 0w = marking code for sc654 yw = date code
3 exceeding the above specifi cations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters specifi ed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114 (2) v f(max) = 1.0v when v in = 2.9v, higher v in supports higher v f(max) (3) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb per jesd51 standards. absolute maximum ratings in, out (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 c1+, c2+ (v) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v out + 0.3) pin voltage all other pins (v) . . . . . . . . -0.3 to (v in + 0.3) out short circuit duration . . . . . . . . . . . . . . . . con tinuous esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 unless otherwise noted, t a = +25c for typ, -40c to +85c for min and max, t j(max) = 125c, v in = 3.7 v, c in = c 1 = c 2 = c out = 2.2f (esr = 0.03) (1) electrical characteristics recommended operating conditions ambient temperature range (c) . . . . . . . . -40 t a +85 input voltage (v) . . . . . . . . . . . . . . . . . . . . . . . 2.9 v in 5.5 output voltage (v) . . . . . . . . . . . . . . . . . . . . . 2.5 v out 5.25 voltage diff erence between any two leds (v). . v f < 1.0 (2) thermal information thermal resistance, junction to ambient (3) (c/w) . . 127 maximum junction temperature (c) . . . . . . . . . . . . . . . +150 storage temperature range (c) . . . . . . . . . . . -65 to +150 peak ir refl ow temperature (10s to 30s) (c) . . . . . . +260 sc654 parameter symbol conditions min typ max units shutdown current i q(off) 0.1 2 a total quiescent current i q all outputs disabled, spif = v in (2) 60 100 a charge pump enabled, 1x mode, all leds on, i bln = 0.5ma 1.8 ma charge pump in 1x mode, 2.9v 2.9v, sum of all active led currents, v out(max) = 4.2v 150 ma backlight current setting i bln nominal setting for bl1 thru bl6 0 25 ma backlight current matching i bl-bl i bln = 12ma (3) -3.5 0.5 +3.5 % backlight current accuracy i bl_acc i bln = 12ma -8 1.5 +8 %
4 electrical characteristics (continued) sc654 parameter symbol conditions min typ max units 1x mode to 1.5x mode falling transition input voltage v trans1x i out = 60ma, i bln = 10ma, v out = 3.2v 3.26 v 1.5x mode to 1x mode hysteresis v hyst1x i out = 60ma, i bln = 10ma, v out = 3.2v 250 mv 1.5x mode to 2x mode falling transition input voltage v trans1.5x i out = 60ma, i bln = 10ma, v out = 4.0v (4) 3.07 v current sink off -state leakage current i bln(off ) v in = v bln = 4.2v 0.1 1 a charge pump frequency f pump v in = 3.2v 250 khz output short circuit current limit i out(sc) out pin shorted to gnd 60 ma v out > 2.5v 300 under voltage lockout v uvlo-off increasing v in 2.7 v v uvlo-hys hysteresis 800 mv over-voltage protection v ovp out pin open circuit, v out = v ovp , rising threshold 5.7 6.0 v over-temperature t ot rising temperature 160 c ot hysteresis t ot-hys 20 c
5 electrical characteristics (continued) sc654 parameter symbol conditions min typ max units sempulse interface input high threshold v ih v in = 5.5v 1.6 v input low threshold v il v in = 2.9v 0.4 v input high current i ih v in = 5.5v -1 +1 a input low current i il v in = 5.5v -1 +1 a start up time (5) t su only required when leaving shutdown mode 1 ms bit pulse duration (6) t hi 0.75 250 s duration between pulses (6) t lo 0.75 250 s hold time - address (6) t holda software limit spif must be held high for this amount of time to latch the data 550 5000 s hold time - data (6) t holdd software limit spif must be held high for this amount of time to latch the address 550 s bus reset time (6) t br software limit spif must be held high for this amount of time to force a bus system reset 12 ms shutdown time (7) t sd software limit spif must be held low for this amount of time to disable device 10 ms notes: (1) capacitors are mlcc of x5r type. production tested with higher value capacitors than the application requires (2) spif is high for more than 10ms to place serial bus in standby mode (3) current matching is defi ned as [i bl(max) - i bl(min ] / [i bl(max) + i bl(min) ]. (4) test voltage is v out = 4.0v a relatively extreme led voltage to force a transition during test. typically v f = 3.2v for white leds. (5) the sempulse start-up time is the minimum time that the spif pin must be held high to enable the part before starting commu nication. (6) the source driver used to provide the sempulse output must meet these limits. (7) the sempulse shutdown time is the minimum time that the spif pin must be pulled low to shut the part down.
6 typical characteristics sc654 all data taken with t a = +25 c, v in = 3.7v, c in = c 1 = c 2 = c out = 2.2f (esr = 0.03) unless otherwise noted. backlight effi ciency (6 leds) 25ma each 50 60 70 80 90 100 2.7 3 3.3 3.6 3.9 4.2 v in (v) efficiency (%) c in = c out = 4.7 f, v out = 3.55v 50 60 70 80 90 100 2.7 3 3.3 3.6 3.9 4.2 v in (v) efficiency (%) v out = 3.45v -3 -2 -1 0 1 2 3 2.7 3 3.3 3.6 3.9 4.2 c in = c out = 4.7 f v in (v) matching (%) 50 60 70 80 90 100 2.7 3 3.3 3.6 3.9 4.2 v in (v) efficiency (%) v out = 3.23v -3 -2 -1 0 1 2 3 2.7 3 3.3 3.6 3.9 4.2 v in (v) matching (%) backlight matching (6 leds) 4.5ma each -3 -2 -1 0 1 2 3 2.7 3 3.3 3.6 3.9 4.2 v in (v) matching (%) backlight effi ciency (6 leds) 12ma each backlight matching (6 leds) 12ma each backlight matching (6 leds) 25ma each backlight effi ciency (6 leds) 4.5ma each
7 typical characteristics (continued) sc654 1ms/div output short circuit current limit v out (1v/div) i out (50ma/div) backlight accuracy (6 leds) 12ma each -8 -6 -4 -2 0 2 4 6 8 2.7 3 3.3 3.6 3.9 4.2 a cc max % a cc min % v in (v) accuracy (%) ripple 2x mode 20s/div v in (100mv/div) v out (100mv/div) i bl (10ma/div) c in = c out = 4.7f, v in = 2.9v, 6 leds 15ma each ripple 1x mode 20s/div v in (100mv/div) v out (100mv/div) i bl (10ma/div) c in = c out = 4.7f, 6 leds, 15ma each ripple 1.5x mode 20s/div v in (100mv/div) v out (100mv/div) i bl (10ma/div) output open circuit protection 20s/div v bl (500mv/div) v out (1v/div) i bl (10ma/div) 0 0 c in = c out = 4.7f, v in = 2.9v, 6 leds, 15ma each 0
8 pin descriptions sc654 pin # pin name pin function 1 bl3 current sink output for main backlight led 3 leave this pin open if unused 2 bl4 current sink output for main backlight led 4 leave this pin open if unused 3 bl5 current sink output for main backlight led 5 leave this pin open if unused 4 bl6 current sink output for main backlight led 6 leave this pin open if unused 5 spif sempulse single wire interface pin used to enable/disable the device and to confi gure all regis- ters (refer to register map and sempulse interface sections) 6 gnd ground pin 7 c2- negative connection to bucket capacitor 2 8 c1- negative connection to bucket capacitor 1 9 c1+ positive connection to bucket capacitor 1 10 c2+ positive connection to bucket capacitor 2 11 out charge pump output all led anode pins should be connected to this pin 12 in battery voltage input 13 bl1 current sink output for main backlight led 1 leave this pin open if unused 14 bl2 current sink output for main backlight led 2 leave this pin open if unused
9 block diagram sc654 oscillator current setting dac sempulse digital interface and logic control fractional charge pump (1x, 1.5x, 2x) c1+ c1- c2+ c2- out bl1 bl2 bl3 bl4 in spif gnd 9 7 10 8 12 5 6 11 13 14 1 2 bl5 bl6 3 4
10 applications information sc654 general description this design is optimized for handheld applications sup- plied from a single li-ion cell and includes the following key features: a high effi ciency fractional charge pump that supplies power to all leds six matched current sinks that control led back- lighting current, providing 0ma to 25ma per led leds can be grouped in up to three indepen- dently controlled banks high current fractional charge pump the backlight outputs are supported by a high effi ciency, high current fractional charge pump output. the charge pump multiplies the input voltage by 1x, 1.5x, or 2x. the charge pump switches at a fi xed frequency of 250khz in 1.5x and 2x modes and is disabled in 1x mode to save power and improve effi ciency. the mode selection circuit automatically selects the mode as 1x, 1.5x, or 2x based on circuit conditions such as led voltage, input voltage, and load current. the 1x mode is the most effi cient of the three modes, followed by 1.5x and 2x modes. circuit conditions such as low input voltage, high output current, or high led voltage place a higher demand on the charge pump output. a higher numerical mode (1.5x or 2x) may be needed momentarily to main- tain regulation at the out pin during intervals of high demand. the charge pump responds to momentary high demands, setting the charge pump to the optimum mode to deliver the output voltage and load current while opti- mizing effi ciency. hysteresis is provided to prevent mode toggling. the charge pump requires two bucket capacitors for proper operation. one capacitor must be connected between the c1+ and c1- pins and the other must be connected between the c2+ and c2- pins as shown in the typical application circuit diagram. these capacitors should be equal in value, with a minimum capacitance of 1f to support the charge pump current requirements. the device also requires at least 1f of capacitance on the in pin and at least 1f of capacitance on the out ? ? ? pin to minimize noise and support the output current requirements of up to 90ma. for output currents higher than 90ma, a nominal value of 4.7f is recommended for c out and c in . capacitors with x7r or x5r ceramic dielectric are strongly recommended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coeffi cients make them unsuitable for this application. it is important to ensure the minimum capacitance value of each capacitor does not drop below 1f. this may require the use of 2.2f capacitors to be sure that the degradation of capacitance due to dc voltage does not cause the capacitance to go below 1f. led backlight current sinks the backlight current is set via the sempulse interface. the current is regulated to one of 29 values between 0ma and 25ma. the step size varies depending upon the current setting. between 0ma and 5ma, the step size is 0.5ma. the step size increases to 1ma for settings between 5ma and 21ma. steps are 2ma between 21ma and 25ma. the variation in step size allows fi ner adjustment for dimming functions in the low current setting range and coarse adjustment at higher current settings where small current changes are not visibly noticeable in led brightness. a zero setting is also included to allow the current sink to be disabled by writing to either the enable bit or the current setting register for maximum fl exibility. all backlight current sinks have matched currents, even when there is a variation in the forward voltages (v f ) of the leds. a v f diff erence of 1.0v is supported when the input voltage is at 2.9v. higher v f led mis-match is sup- ported when v in is higher than 2.9v. all current sink outputs are compared and the lowest output is used for setting the voltage regulation at the out pin. this is done to ensure that suffi cient bias exists for all leds. the backlight leds default to the off state upon power- up. for backlight applications using less than six leds, any unused output must be left open and the unused led must remain disabled. when writing to the backlight enable register, a zero (0) must be written to the corresponding bit of any unused output.
11 applications information (continued) sc654 backlight quiescent current the quiescent current required to operate all backlights is reduced when the backlight current is set to 4.0ma or less. this feature results in higher effi ciency under light-load conditions. further reduction in quiescent current will result from using fewer than the maximum number of leds. led banks the leds can be grouped in up to three independently controlled led banks. using the sempulse interface, the six led drivers can be grouped as described in the backlight grouping confi guration subsection. the banks can be used to provide up to three different current options. this can be useful for controlling keypad, display, and auxiliary backlight operation from one sc654 device. the led banks provide versatility by allowing backlights to be controlled independently. for example, applications that have a main and sub display may also need to supply an indicator led. the three bank option allows the sc654 to control each function with diff erent current settings. another application involves backlighting two displays and a keypad, each requiring diff erent brightness settings. a third scenario requires supplying diff erent brightness levels to diff erent types of leds (such as rgb) to create display eff ects. in all applications, the brightness level for each led can be set independently. backlight fade-in / fade-out function the sc654 contains bits that control the fade state of the main bank. when enabled, the fade function causes the backlight settings to step from their current state to the next programmed state as soon as the new state is stored in its register. for example, if the backlight is set at 25ma and the next setting is the off state, the backlight will step from 25ma down to 0ma using all settings at the fade rate specifi ed by the bits in register 04h. the same is true when turning on or increasing the backlight current the backlight current will step from the present level to the new level at the step rate defi ned in register 04h. this process applies to the main display only. the fade rate may be changed dynamically when a fade operation is active by writing new values to the fade reg- ister. when a new backlight level is written during an ongoing fade operation, the fade will be redirected to the new value from the present state. an ongoing fade opera- tion may be cancelled by disabling fade which will result in the backlight current changing immediately to the fi nal value. if fade is disabled, the current level will change immediately without the fade delay. the state diagram in figure 1 describes the fade opera- tion. more details can be found in the register map section. write fade=0 write new bright level fade=0 no change write fade=0 fade=1 fade processing (1) write new bright level write new bright level fade is redirected toward the new value from current state fade begins fade ends write fade=1 fade=1 fade=0 immediate change to new bright level fade=0 write fade=1 no change write fade=1 no change immediate change to new bright level write new fade rate continue fade using new rate note: (1) when the data in backlight enable register 00h is not 00h figure 1 state diagram for fade function fade-in from off state when the initial state of the backlight enable register is 00h (all backlights off ), fading to an on state is accom- plished by following the steps listed in table 1. following these steps explicitly will ensure that the fade-in opera- tion will proceed with no interruption at the rate specifi ed in the main fade register (04h). this procedure must be followed regardless of which backlight grouping confi gu-
12 applications information (continued) sc654 ration is being used. note that it is only necessary to set the blen bits for the main display. table 1 fade-in from off state command sequence action data disable fade 1. write to register 04h 00h set main back- lights to 0.5ma 2. write to register 01h 04h enable fade 3. write to register 04h 01h, 02h, or 03h (but not 00h) set blen bits 4. write to register 00h any value 01h through 3fh (but not 00h) set new value of backlight current 5. write to register 01h any value 05h through 1fh fade-out from any on state to off state fading the backlight leds from any active state to the off state follows a simple procedure. the sequence of com- mands for this action is shown in table 2. following these steps explicitly will ensure that the fade-out operation will proceed with no interruption at the rate specifi ed in the main fade register (04h). this procedure must be followed regardless of the backlight grouping confi guration. table 2 fade-out from any on state to off state command sequence action data enable fade 1. write to register 04h 01h, 02h, or 03h (but not 00h) set main back- lights to 0ma 2. write to register 01h 00h fading between diff erent on states fading from one backlight level to another (up or down) also follows a simple procedure. the sequence of com- mands for this action is shown in table 3. following these steps explicitly will ensure that the fade-in/fade-out oper- ation will proceed with no interruption at the rate specifi ed in the main fade register (04h). this procedure must be followed regardless of the backlight grouping confi guration. table 3 fading between diff erent on states command sequence action data enable fade 1. write to register 04h 01h, 02h, or 03h (but not 00h) set new value of backlight current 2. write to register 01h any value 05h through 1fh additional information for more details about the fade-in/fade-out function, refer to the sc654 backlight driver software users guide and sempulse interface specifi cation document and to the associated software drivers available for this device (contact your sales offi ce for more details). shutdown mode the device is disabled when the spif pin is held low for the shutdown time specifi ed in the electrical characteris- tics section. all registers are reset to default condition at shutdown. sleep mode when all leds are disabled, sleep mode is activated. this is a reduced current mode that helps minimize overall current consumption by disabling the clock and the charge pump while continuing to monitor the serial inter- face for commands. an additional current savings can be obtained by putting the serial interface in standby mode (see sempulse interface, standby mode). protection features the sc654 provides several protection features to safe- guard the device from catastrophic failures. these features include: output open circuit protection over-temperature protection charge pump output current limit led float detection output open circuit protection over-voltage protection (ovp) at the out pin prevents the charge pump from producing an excessively high output voltage. in the event of an open circuit between the out pin and all current sinks (no loads connected), the charge pump runs in open loop and the voltage rises ? ? ? ?
13 applications information (continued) sc654 up to the ovp limit. ovp operation is hysteretic, meaning the charge pump will momentarily turn off until v out is suffi ciently reduced. the maximum ovp threshold is 6.0v, allowing the use of a ceramic output capacitor rated at 6.3v. over-temperature protection the over-temperature (ot) protection circuit prevents the device from overheating and experiencing a catastrophic failure. when the junction temperature exceeds 160 c, the device goes into thermal shutdown with all outputs dis- abled until the junction temperature is reduced. all regis- ter information is retained during thermal shutdown. hysteresis of 20c is provided to ensure that the device cools suffi ciently before re-enabling. charge pump output current limit the device limits the charge pump current at the out pin. if the out pin is shorted to ground, or v out is lower than v uvlo , the typical output current limit is 60ma. the output current is limited to 300ma when over loaded resistively with v out greater than 2.5v. led float detection float detect is a fault detection feature of the led back- light outputs. if an output is programmed to be enabled and an open circuit fault occurs at any backlight output, that output will be disabled to prevent a sustained output ovp condition from occurring due to the resulting open loop. float detect ensures device protection but does not ensure optimum performance. unused led outputs must be disabled to prevent an open circuit fault from occurring. thermal management although the sc654 can provide up to 150ma output current, the maximum thermal temperature and the thermal resistance ( ja ) of the package and layout may limit the output current. thermal resistance can be lowered by following the recommended layout guidelines in pcb layout considerations, as illustrated in figure 2. pcb layout considerations following fundamental layout rules is critical for achieving the performance specifi ed in the electrical characteristics table. the following guidelines are recommended when developing a pcb layout: place all capacitors (c1, c2, cin, and cout) as close to the device as possible. all charge pump current passes through the in/ out and the bucket capacitor connection pins. ensure that all connections to these pins make the of wide traces so that the resistive drop on each connection is minimized. make all ground connections to a solid ground plane as shown in the example layout . figure 2 suggested layout ? ? ?
14 sc654 sempulse tm interface introduction sempulse is a write-only single wire interface. it provides the capability to access up to 32 registers that control device functionality. two sets of pulse trains are transmit- ted via the spif pin. the fi rst pulse set is used to set the desired address. after the bus is held high for the address hold period, the next pulse set is used to write the data value. after the data pulses are transmitted, the bus is held high again for the data hold period to signify the data write is complete. at this point the device latches the data into the address that was selected by the fi rst set of pulses. see the sempulse timing diagrams for descriptions of all timing parameters. chip enable/disable the device is enabled when the sempulse interface pin (spif) is pulled high for greater than t su . if the spif pin is pulled low again for more than t sd , the device will be disabled. address writes the fi rst set of pulses can range between 0 and 31 (or 1 to 32 rising edges) to set the desired address. after the pulses are transmitted, the spif pin must be held high for t holda to signal to the slave device that the address write is fi nished. if the pulse count is between 0 and 31 and the line is held high for t holda , the address is latched as the destination for the next data write. if the spif pin is not held high for t holda , the slave device will continue to count pulses. note that if t holda exceeds its maximum specifi ca- tion, the bus will reset. this means that the communication is ignored and the bus resumes monitoring the pin, expecting the next pulse set to be an address. if the total exceeds 31 pulses, spif must be held high until the bus reset time t br is exceeded before commencing communication. data writes after the bus has been held high for the minimum address hold period, the next set of pulses are used to write the data value. the total number of pulses can range from 0 to 63 (or 1 to 64 rising edges) since there are a total of 6 register bits per register. just like with the address write, the data write is only accepted if the bus is held high for t holdd when the pulse train is completed. if the proper hold time is not received, the interface will keep counting pulses until the hold time is detected. if the total exceeds 63 pulses, the write will be ignored and the bus will reset after the next valid hold time is detected. after the bus has been held high for t holdd , the bus will expect the next pulse set to be an address write. note that this is the same eff ect as the bus reset that occurs when t holda exceeds its maximum specification. for this reason, there is no maximum limit on t holdd the bus simply waits for the next valid address to be transmitted. multiple writes it is important to note that this single-wire interface requires the address to be paired with its corresponding data. if it is desired to write multiple times to the same address, the address must always be re-transmitted prior to the corresponding data. if it is only transmitted one time and followed by multiple data transmissions, every other block of data will be treated like a new address. the result will be invalid data writes to incorrect addresses. note that multiple writes only need to be separated by the minimum t holdd for the slave to interpret them cor- rectly. as long as t holda between the address pulse set and the data pulse set is less than its maximum specifi cation but greater than its minimum, multiple pairs of address and data pulse counts can be made with no detrimental eff ects. standby mode once data transfer is completed, the spif line must be returned to the high state for at least 10ms to return to the standby mode. in this mode, the spif line remains idle while monitoring for the next command. this mode allows the device to minimize current consumption between commands. once the device has returned to standby mode, the bus is automatically reset to expect the address pulses as the next data block. this safeguard is intended to reset the bus to a known state (waiting for the beginning of a write sequence) if the delay exceeds the reset threshold.
15 sc654 sempulse tm interface (continued) sempulse timing diagrams the sempulse single wire interface is used to enable or disable the device and confi gure all registers (see figure 3). the timing parameters refer to the digital i/o electrical specifi cations. t lo t hi t = t su t = t holda t = t holdd address is set data is written spif up to 32 rising edges (0 to 31 pulses) up to 64 rising edges (0 to 63 pulses) figure 3 uniform timing diagram for sempulse communication timing example 1 in this example (see figure 4), the slave chip receives two sets of pulses to set the address and data, and the pulses expe- rience interrupts that cause the pulse width to be nonuniform. note that as long as the maximum high and low times are satisfi ed and the hold times are within specifi cation, the data transfer is completed regardless of the number of interrupts that delay the transmission. t hi t lo t < t himax t < t lomax t = t su data written is 000011 spif t = t holda t = t holdd address is set to register 02h figure 4 sempulse data write with non-uniform pulse widths timing example 2 in this example (see figure 5), the slave chip receives two sets of pulses to set the address and data, but an interrupt occurs during a pulse that causes it to exceed the minimum address hold time. the write is meant to be the value 03h in register 05h, but instead it is interpreted as the value 02h written to register 02h. the extended pulse that is delayed by the interrupt triggers a false address detection, causing the next pulse set to be interpreted as the data set. to avoid any problems with timing, make sure that all pulse widths comply with their timing requirements as outlined in this datasheet. data written is 000010 spif t > t himax t = t holdd address is set to register 02h interrupt duration t = t holda address is set to register 03h (address and data are now out of order) figure 5 faulty sempulse data write due to extended interrupt duration
16 register map (1) sc654 address d5 d4 d3 d2 d1 d0 reset value description 00h blen6 blen5 blen4 blen3 blen2 blen1 00h backlight enable 01h 0 (2) mbl4 mbl3 mbl2 mbl1 mbl0 00h main backlight current 02h 0 (2) sbl4 sbl3 sbl2 sbl1 sbl0 00h sub backlight current 03h 0 (2) tbl4 tbl3 tbl2 tbl1 tbl0 00h third backlight current 04h 0 (2) 0 (2) 0 (2) 0 (2) mfade1 mfade0 00h main fade 05h 0 (2) 0 (2) 0 (2) mb2 mb1 mb0 00h backlight grouping confi guration defi nition of registers and bits bl enable control register (00h) this register enables each individual led. blen6 blen1 [d5:d0] these active high bits enable the six backlight drivers. each led can be controlled independently. notes: (1) all registers are write-only. (2) 0 = always write a 0 to these bits
17 register and bit defi nitions (continued) main backlight current control register (01h) this register is used to set the currents for the backlight current sinks assigned to the main backlight group. this group can also be used to control red leds for limited rgb control. these current sinks need to be enabled in the backlight enable control register to be active. bit d5 this bit is unused and is always a zero, so the maximum pulse count for this register is 31. mbl4 mbl0 [d4:d0] these bits are used to set the current for the main back- light current sinks. all enabled main backlight current sinks will sink the same current, as shown in table 4. table 4 main backlight current settings mbl4 mbl3 mbl2 mbl1 mbl0 backlight current (ma) 00000 0 0 0 0 0 1 see note 1 0 0 0 1 0 see note 1 0 0 0 1 1 see note 1 00100 0.5 00101 1.0 00110 1.5 00111 2.0 01000 2.5 01001 3.0 01010 3.5 01011 4.0 01100 4.5 01101 5.0 01110 6.0 01111 7.0 10000 8.0 10001 9.0 10010 10 10011 11 10100 12 10101 13 10110 14 10111 15 11000 16 11001 17 11010 18 11011 19 11100 20 11101 21 11110 23 11111 25 (1) reserved for future use sc654
18 register and bit defi nitions (continued) sub backlight current control register (02h) this register is used to set the currents for the backlight current sinks assigned to the sub backlight group. this group can also be used to control green leds for limited rgb control. these current sinks need to be enabled in the backlight enable control register to be active. bit d5 this bit is unused and is always a zero, so the maximum pulse count for this register is 31. sbl4 sbl0 [d4:d0] these bits are used to set the current for the sub backlight current sinks. all enabled sub backlight current sinks will sink the same current, as shown in table 5. table 5 sub backlight current settings sbl4 sbl3 sbl2 sbl1 sbl0 backlight current (ma) 00000 0 0 0 0 0 1 see note 1 0 0 0 1 0 see note 1 0 0 0 1 1 see note 1 00100 0.5 00101 1.0 00110 1.5 00111 2.0 01000 2.5 01001 3.0 01010 3.5 01011 4.0 01100 4.5 01101 5.0 01110 6.0 01111 7.0 10000 8.0 10001 9.0 10010 10 10011 11 10100 12 10101 13 10110 14 10111 15 11000 16 11001 17 11010 18 11011 19 11100 20 11101 21 11110 23 11111 25 (1) reserved for future use sc654
19 register and bit defi nitions (continued) third backlight current control register (03h) this register is used to set the currents for the backlight current sinks assigned to the third backlight group. this group can also be used to control blue leds for limited rgb control. these current sinks need to be enabled in the backlight enable control register to be active. bit d5 this bit is unused and is always a zero, so the maximum pulse count for this register is 31. tbl4 tbl0 [d4:d0] these bits are used to set the current for the third back- light current sinks. all enabled third backlight current sinks will sink the same current, as shown in table 6. table 6 third backlight current control bits tbl4 tbl3 tbl2 tbl1 tbl0 backlight current (ma) 00000 0 0 0 0 0 1 see note 1 0 0 0 1 0 see note 1 0 0 0 1 1 see note 1 00100 0.5 00101 1.0 00110 1.5 00111 2.0 01000 2.5 01001 3.0 01010 3.5 01011 4.0 01100 4.5 01101 5.0 01110 6.0 01111 7.0 10000 8.0 10001 9.0 10010 10 10011 11 10100 12 10101 13 10110 14 10111 15 11000 16 11001 17 11010 18 11011 19 11100 20 11101 21 11110 23 11111 25 (1) reserved for future use sc654
20 register and bit defi nitions (continued) sc654 main fade control (04h) this register sets the fade status and rate for the main backlight group. bits [d5:d2] these bits are unused and are always zeros, so the maximum pulse count for this register is 3. mfade1, mfade0[d1:d0] these bits are used to enable and set the rise/fall rate between two backlight currents as follows in table 7. table 7 main display fade control bits mfade1 mfade0 fade feature rise/fall rate (ms/step) 0 0 off 01 8 10 16 11 32 the number of steps used to change the backlight current will be equal to the change in binary count of bits mbl[4:0]. when a new backlight current is set, the backlight current will change from its current value to a new value set by bits mbl[4:0] at the rate determined by mfade1 and mfade0 bits. the total fade time is determined by the number of steps between old and new backlight values, in table 4, multiplied by the rate of fade in ms/step. backlight grouping confi guration (05h) this register assigns the leds to the back light bank confi gurations. bits [d5:d3] these bits are unused and are always zeros, so the maximum pulse count for this register is 7. mb2, mb1 and mb0 [d2:d0] these bits are used to set the number of led drivers dedi- cated to each backlight group. this allows the device to drive up to three different sets of leds with different current settings. note that any driver assigned to any led group can still be disabled independently if not needed. the code set by these bits determines how the led drivers are assigned among the three led groups according to the assignments listed in table 8. default state for each of these three bits is 0 (all leds assigned to main display). table 8 backlight grouping confi guration mb2 mb1 mb0 main display led drivers sub display led drivers third display led drivers 0 0 0 bl1-bl6 0 0 1 bl1-bl3 bl4-bl6 0 1 0 bl1-bl2 bl3-bl4 bl5-bl6 011 bl1-bl2, bl5-bl6 bl3 bl4 1 0 0 bl1-bl3 bl4-bl5 bl6 1 0 1 bl1-bl4 bl5 - bl6 1 1 x bl1-bl5 bl6
21 outline drawing mlpq-ut-14 2x2 .020 .006 .010 .000 .077 n aaa bbb l e d e a2 a1 b .012 .016 bsc .004 .003 14 .008 (.006) .079 - min dim nom inches - 0.60 0.50 0.40 bsc (0.152) 0.25 14 0.10 0.08 0.30 0.15 1.95 0.00 0.20 2.00 - 0.35 0.25 2.05 0.05 nom millimeters min max 1.95 2.00 2.05 .077 .079 .081 l1 .014 .016 .018 0.35 0.40 0.45 a1 bxn 0.20 0.15 notes: controlling dimensions are in millimeters (angles in degrees). 1. pin 1 indicator (laser mark) a b aaa c c seating plane bbb c a b 1 n d e a a2 e/2 e e/2 d/2 .010 max dimensions .014 .002 .024 .081 a - l1 lxn sc654
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information 22 land pattern mlpq-ut-14 2x2 millimeters dim inches (.079) x y z g c p .008 .102 .024 .016 .055 0.40 0.20 1.40 (2.00) 2.60 0.60 dimensions square package - dimensions apply in both " x " and " y " directions. controlling dimensions are in millimeters (angles in degrees). this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 3. 1. 2. y p (c) g x 4. pin 1 pad can be shorter than the actual package lead to avoid solder bridging between pins 1 & 14. r .004 0.10 r z sc654

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